1. Technical Field
The present invention relates to a data output strobe signal generating circuit and a semiconductor memory apparatus having the same, and more particularly, to a circuit for generating a data output strobe signal that is enabled at a correct timing and to a semiconductor memory apparatus having the same.
2. Related Art
In general, semiconductor memory apparatuses include data output buffers for a data output operation. The data output buffer outputs data transmitted through a global line in synchronization with a data output strobe signal. The data output strobe signal is generated from a clock having a high level at the rising edge timing of a DLL (delay locked loop) clock (hereinafter, referred to as a rising clock) or a clock having a high level at the falling edge timing of the DLL clock (hereinafter, referred to as a falling clock). In order to generate the data output strobe signal, the semiconductor memory apparatuses include data output strobe signal generating circuits.
In general, a DLL circuit generates a DLL clock having a phase that leads the phase of an external clock by a predetermined amount of time in order to compensate for the delay of a clock by internal delay elements provided in a semiconductor memory apparatus. The DLL circuit divides the DLL clock into a rising clock and a falling clock and adjusts the duty ratio of each of the clocks to 50:50. Therefore, ideally, the duty ratio of each of the rising clock and the falling clock transmitted to the data output strobe signal generating circuit should be 50:50. However, actually, the duty ratio of each of the rising clock and the falling clock varies due to resistance and noise existing on a clock transmitting line. If the data output strobe signal is generated under the conditions when the duty ratio of each of the rising clock and the falling clock is not 50:50, an enable period of the data output strobe signal varies, which makes it difficult to exactly control the operation of the data output buffer. At worst, a data output operation may not be performed.
However, the data output strobe signal generating circuit of the semiconductor memory apparatus according to the related art generates the data output strobe signal from the rising clock and the falling clock that do not have a correct duty ratio. Therefore, it is difficult for the data output strobe signal generating circuit to generate a data output strobe signal having a correct enable period. As a result, the semiconductor memory apparatus is more likely to operate erroneously during data output, which makes it difficult to perform a correct data output operation. That is, the reliability of the data output operation of the semiconductor memory apparatus is lowered.